Integrated memories, for example, in the form of DRAMs (Dynamic Random Access Memories), are generally subject to comprehensive functional tests in the fabrication process. Inter alia, the functional tests serve for identifying defective memory cells or defective column lines or row lines. As the memory size increases, the costs of functional tests make up an ever greater proportion of the overall production costs of a memory. In order to lower the test costs, therefore, methods such as test modes for compressing data or additional test logic, for example, in the form of BIST (Built-In Self-Test), are increasingly being developed.
Integrated memories generally have redundant memory cells for repairing defective memory cells. The redundant memory cells are usually combined to form redundant row lines or redundant column lines that can replace regular lines having defective memory cells in address terms. As a result, it is possible for integrated memories, in particular, in the form of DRAMs, to be fabricated economically with the integration densities that are achieved nowadays. An integrated memory is tested, for example, by an external test device and a programming of redundant elements is subsequently performed based on a redundancy analysis. In order to be able to carry out a repair of a memory in a targeted manner, it is necessary, in corresponding tests or test sequences, to identify all defects and store them together with the associated address on the external test system. For this purpose, the addresses of those tested memory cells which have been detected as defective are stored in a defect address memory, i.e., Fail Bit Map, in order to replace these memory cells by defect-free redundant memory cells in a subsequent step based on stored addresses. The repair solution specific to each memory can subsequently be calculated in the test system based on the fail bit map.
In order to minimize the test costs per memory chip, the memory chips are increasingly tested in parallel. This trend is supplemented by the increasing use of test circuits that are provided on the memory chip, such as, for example, circuits for carrying out BIST or compressing test modes. Such circuits support an externally connected test unit for functional testing of the memory chip and thereby reduce the test cycle times without a new, more complex tester equipment having to be used for this purpose. With the use of a BIST, the test control (i.e., address and data generation, command sequence) is generally effected completely in the memory chip. However, the test cycle times are furthermore primarily limited by the fact that the calculation of the repair solution upon establishing functional defects in the memory chip still has to be effected externally. Therefore, it is necessary to transmit the defect data to an external unit even in the case of a BIST-based test cycle. The external unit receives the defect data and calculating a repair solution therefrom.
An integrated memory and a method for functional testing of an integrated memory by which to accelerate a test cycle for functional testing of the memory, are desirable.